It is the nature of the computer system development industry to require an exponential performance advantage over the generations while maintaining or decreasing system costs. In particular, telecommunications and networking computing systems additionally benefit from a reduction in the board size and an increase in system capabilities.
Computer system processors and peripherals continually benefit from the aforementioned generational performance advantage. This phenomenon is driven by improvements in process technology. In order to realize a proportional system wide improvement in performance, the connection fabric must improve along with the improvements in processors and peripherals.
A hierarchy of shared buses is a common fabric structure. Levels of performance required for the multiple devices in the system typically differentiate this hierarchy. A given bus is associated with one such level. Bus bridges connect the buses. In this structure a low performance device does not burden a high performance device.
This type of structure benefits from an increase in bus frequency, a wider interface, pipelined transactions and out of order completion capability. However. these techniques are well known, and are exploited to their full potential. Further increases in bus width will reduce maximum bus frequency due to skew effects i.e. as the data-path is altered to include a greater number of data bits, the skew, between those individual bits, originating in the transmission medium, becomes increasingly severe. A wider bus will also increase pin count. This will affect cost, and limit the interfaces on a device.
Furthermore, the maximization of bus frequency and width is incompatible with a many-device connection. Finally, it would be advantageous to increase the number of devices capable of direct communication.
Therefore, point to point, packet switched, fabric architectures have emerged as an alternative to the aforementioned bus structures. Such an architecture is beneficial in network equipment, storage subsystems and computing platforms. Networks of this architecture transmit encapsulated address, control and data packets from the source ports across a series of routing switches or gateways to addressed destinations. The switches and gateways of the switching fabric are capable of determining from the address and control contents of a packet, what activities must be performed. The architecture is capable of providing an interface for processors, memory modules and memory mapped I/O devices.
In a typical packet switched interconnect, the functionality is organized into a hierarchy of multiple layers. The disposition of typical layers apportions the functions most related to control and compatibility to the highest layers. The most rudimentary and device oriented considerations are apportioned to the lowest layer. The physical layer is the lowest or most physically fundamental layer.
Physical layer specifications define the interface between devices including packet transport mechanisms, flow control, and electrical characteristics.
For a packet switching network to be highly efficient, the physical layer of the network must strive to meet certain criteria, and for functions of the physical layer to be efficiently carried out.
Specifically:
The transmitter and receiver must establish the data integrity of the channel and ideally should do so without additional hardware or cumbersome handshaking.
The physical layer should incorporate boundary scan testing in a manner that does not unnecessarily skew time sensitive signals i.e. clocks.
Should the physical layer incorporate delay lines, no significant jitter should be introduced due to variances in the manufacturing process.
Should the network define words that are multiple bytes in length, any corresponding word or byte frame signals, ideally do not require handshaking or additional pin count for synchronization.
Should a physical layer receive clock incorporate multiple delay lock loops (DLLs) for synchronizing with a transmit clock, it should be possible to allow adjustments of a fraction of the finest delay lock loop.
The problem with addressing these issues with 0.13_m CMOS is that the power supply voltage is 1.2V and this creates a real problem for the non logic designer as most of the techniques used in 3.3V or even 2.5V such as cascoding current sources (to improve output impedance and gain of circuits) either do not work well (or do not work at all).
In many kinds of circuits, there is a fundamental set of contradictory requirements: high speed operation, rail to rail inputs and or outputs, and low voltage operation. Some examples of these are: DLLs, PLLs, charge pumps, op amps, IO pads. In all these cases, the biasing is done with current sources and circuit performance is often limited by these current sources.
There is a need for improvements in the physical layer of a packet switched fabric, to address these concerns, in order to ensure that the fabric is highly efficient. In particular there is a need for increased co-ordination and synchronization between transmission and reception interfaces while maintaining a minimum increase in pin count, clock skew, and cycle overhead.
In particular, at 0.13 μm, the power supply voltage is 1.2 V. This present a real problem for a designer of circuits that are not logic circuits because typical techniques used in 3.3 V or even 2.5 V domains either do not work well or do not work at all. For example cascading current sources to improve output impedance and gain circuits. Part of the problem is that in many kinds of circuits there are fundamentally contradictory requirements, such as high speed operation., rail-to-rail inputs and/or outputs, and low voltage operation. For example, these circuits include delay lock loops (DLL), phase lock loops (PLL), charge pumps, operational amplifiers (Op Amps), input/output (I/O) pads.